1. Field of the Invention
The present invention relates to a technique for testing a semiconductor device, in particular, to a technique for evaluating signals with a differential form outputted from a device to be tested.
2. Description of the Related Art
In recent years, differential transmission systems have been widely used among digital home appliances such as TV sets, DVD (Digital Versatile Disc) players, in order to transmit video signals and audio signals at high speeds. The differential transmission systems are expected to be used in data transmission among devices such as memories and CPUs (Central Processing Units) in the near future.
For example, XDR-DRAM (eXtreme Data Rate Dynamic Random Access Memory) transmits bidirectionally a pair of differential signals (hereinafter, simply referred to as differential signals) at a high speed by using single differential signal wires. In the case of testing a device with such a bidirectional differential interface, amplitudes of the differential signals outputted from a device to be tested (DUT) are measured, by which good or bad is determined with respect to the DUT.
FIGS. 1A and 1B are block diagrams illustrating part of the structure of a test apparatus for testing a device with a differential interface. As illustrated in FIG. 1A, a test system 300 is provided with a pin electronics PE and a test fixture TF. A DUT 200 is fixed to a socket board (SB). The pin electronics PE is provided with a differential comparator 110. The differential comparator 110 is also referred to as a timing comparator, which receives differential signals UP/UN outputted from the DUT 200, and determines levels of the differential signals UP/UN at a timing synchronized with the strobe signal. Herein, “P/N” represents a pair of differential signals. A pair of differential signal wires 50P/50N (hereinafter, also referred to collectively as differential signal wires 50) that connects the socket board SB and the pin electronics PE, is provided on the test fixture TF.
FIG. 1B is a circuit diagram illustrating a structure of the differential comparator 110. The differential comparator 110 includes a subtractor 112, a first comparator 114, a second comparator 116, a first latch 118, and a second latch 120. The subtractor 112 generates a difference between the differential signals RP and RN, that is, a differential amplitude signal DA. The first comparator 114 compares the differential amplitude signal DA with a higher threshold voltage VOH. The first latch 118 latches a comparison result SH at a timing of a first strobe signal Hstb. The second comparator 116 compares the differential amplitude signal DA with a lower threshold voltage VOL. The second latch 120 latches a comparison result SL at a timing of a second strobe signal Lstb. Logic values of the data SH and SL indicating the comparison results are determined based on the following equations (1A) and (1B):SH=sign(VOH−(RP−RN))  (1A)SL=sign((RP−RN)−VOL)  (1B)wherein sign(x) is a function value of which is 1 when x>0, and 0 when x<0.
Ideally, lengths of the pair of the differential signal wires 50 formed on the test fixture TF are the same; however, in an actual test apparatus, the lengths thereof are sometimes different. FIGS. 2A and 2B are charts illustrating operation waveforms of the differential comparator 110 in the cases where the lengths of the differential lines are the same or different, respectively. As illustrated in FIG. 2A, in the case where the lengths of the differential signal wires 50 are the same, the differential signals UP/UN outputted from the DUT 200 reach the differential comparator 110 with the same delay tpd (RP/RN).
Transition from the low-level (0) to the high-level (1) of the differential amplitude signal (RP−RN) is taken into consideration. The outputs SH and SL from the two comparators 114 and 116 are latched at timings of the strobe signals Hstb and Lstb, between them a time difference Tcr being present.
Based on a combination of the latched signals (fail signals) FH and FL, a transition time T from a low-level (<VOL) to a high-level (>VOH) of the differential amplitude signal (RP−RN) is determined whether the time T is shorter than a predetermined value Tcr or not. In FIG. 2A, signals FH and FL are both at the low-levels; hence, it is determined that T<Trc holds.
FIG. 2B illustrates the case where the lengths of the differential signal wires 50P/50N are different, and a delay amount of the differential signal UN is longer than that of the differential signal UP, by a predetermined time te. In this case, a waveform of the differential amplitude signal (RP−RN) that is expected to have been outputted properly from the DUT 200 becomes weak within the test apparatus, such that the fail signal FH is determined to be at the high-level and the fail signal FL to be at the low-level; therefore, the transition time T is determined erroneously to be longer than the predetermined value Tcr.
For example, when a variable-length coaxial cable (trombone) is provided on a pathway in series to the test fixture TF, an imbalance between the differential lines can be canceled by changing a length of the coaxial cable. However, the variable-length coaxial cable is expensive and large-sized; hence it is unrealistic that the variable-length coaxial cable is provided to each differential line of the test apparatus, in particular, the test apparatus provided with hundreds to thousands of channels. Further, the variable-length coaxial cable is a device line length of which is changed mechanically, and hence the cable is difficult to be adjusted quickly.
The whole differential signal wires 50 may also be formed by using lines excellent in a symmetrical property, such as twisted pair; however, in the case, when a phase difference or an asymmetric property is present in the differential signals UP/UN from the DUT 200, the signals are averaged during propagation, making it difficult to evaluate a true waveform from the DUT 200 on the side of the test apparatus. It is an original advantage with the differential line that an asymmetric property of waveforms is averaged on the way of the transmission line; however, it becomes a disadvantage from a viewpoint of test apparatuses.
Other techniques to deal with an imbalance between differential line lengths are disclosed in Patent Documents 1 to 3.
A test apparatus for testing a DUT with a bidirectional differential interface is provided with a transmitter and a receiver that are connected to a pair of differential signal wires (hereinafter, also simply referred to as differential signal wires) in common. The transmitter transmits a test pattern to the DUT; and the receiver determines a logical value of the differential signals outputted from the DUT, or checks amplitude of a difference voltage of a pair of the differential signals.
The receiver of the test apparatus is connected to the transmitter on the side of the test apparatus via a pair of the differential signal wires as well as connection to the DUT. Accordingly, it is necessary to design the test apparatus for testing a DUT with a bidirectional differential interface, such that the receiver is not affected by an output from an adjacent transmitter. In some of the Patent Documents (in particular, Patent Documents 5 to 7), a circuit that receives only signals from the other end by canceling transmission signals outputted from itself (hybrid circuit) is disclosed.
[Patent Document 1] U.S. Pat. No. 7,397,289
[Patent Document 2] U.S. Pat. No. 6,909,980 B2
[Patent Document 3] International Patent Publication Pamphlet No. 05/081004
[Patent Document 4] U.S. Pat. No. 7,121,132
[Patent Document 5] Japanese Patent Application Laid-Open No. 2006-23233
[Patent Document 6] Japanese Patent Application Laid-Open No. S47-011702
[Patent Document 7] Japanese Patent Application Laid-Open No. H8-023354
[Patent Document 8] U.S. Pat. No. 2,725,532
[Patent Document 9] U.S. Pat. No. 6,133,725
[Patent Document 10] U.S. Pat. No. 6,563,298
[Patent Document 11] U.S. Pat. No. 7,373,574